This invention principally relates to a bi-directional shift register for shifting data in a forward direction or in a reverse direction.
In general, an address selector may be composed of a bi-directional shift register connected to switching elements which are connected to a data bus line and DRAM memory cells arranged between two paralleling word lines and digit lines in a number corresponding to respective switching elements via the same number of sense amplifiers connected with the switching elements.
The bi-directional shift register here is disposed such that an input signal (REV signal, CLK signal, STA signal) is inputted at a control signal generator, where a different control signal is generated for controlling operation of a predetermined number of flip-flops. An output signal (address selecting signal) is obtained from inner contacts which are not simultaneously at a high level in specific one of respective flip-flops in accordance with the control signal.
By the way, in the case of the bi-directional shift register here, in order to use as an address selector, data is extracted from the inner contacts which are not simultaneously at a high level, and subsequently only an address selecting signal can be extracted from each two flip-flops composing the shift register. A problem arises in terms of integration degree as a semiconductor integrated circuit.
Thereupon, a bi-directional signal transmission circuit network and a bi-directional signal transfer shift register disclosed in Japanese Patent Publication Tokkai Hei 7-13513 (13513/1995) provide two data paths in a bi-directional shift register to implement improvement in the function of the integration degree.
In the case of the bi-directional shift register disclosed in the above described Japanese Patent Publication Tokkai Hei 7-13513, a problem arises that a feature thereof is easily deteriorated on account of the difference in data transfer speed, as will be described later.
It is an object of this invention to provide a bi-directional shift register having a bi-directional shift function without deteriorating data with a reduced number of elements.
It is another object of this invention to provide a bi-directional shift register capable of improving the integration degree as a semiconductor integrated circuit.
According to a first aspect of this invention, there is provided a bi-directional shift register comprising a predetermined number of flip-flops having first switching elements and second switching elements. The first switching elements being controlled to on and off states in accordance with a first control signal, the second switching elements being controlled to on and off states in accordance with a second control signal. A plurality of third switching elements are connected sequentially between the flip-flops to constitute a multistage structure, the third switching elements being controlled to on and off states in accordance with a third control signal which is for use in shifting the data by periodically clocking from a low level to a high level or from a high level to a low level.
The third control signal is a clock signal. The bi-directional shift register further comprises control producing means for producing first fourth though clock signals different from one another in accordance with the clock signal and an REV signal which is for use in controlling a shift direction of data. The control producing means puts the third and the fourth clock signals into a low level and a high level, respectively, to make the first switching elements be open when the data are shifted to the forward direction. The control producing means puts the first and the second clock signals into a low level and a high level, respectively, to make the second switching elements be open when the data are shifted to the reverse direction.
According to a second aspect of this invention, there is provided an address selector comprising the above-mentioned bi-directional shift register. The address selector comprises output means connected to the bi-directional shift and having a plurality of output terminals for making one of the output terminals be a high level to output an output signal as an address select signal.
According to a third aspect of this invention, there is provided an FIFO/LIFO circuit comprising the above-mentioned address selector. The FIFO/LIFO circuit has an FIFO function which sequentially selects an address. Furthermore, the FIFO/LIFO circuit has an LIFO function which sequentially selects an address in reverse order. The output means inputs the REV signal as a selection control signal and connects two sets of lines of the bi-directional shift register to form two groups of output terminals. The output means comprises an output selector circuit for selectively outputting either one of the two groups of output terminals in accordance with the selection control signal.